Latency-Aware Accelerator of SIMECK Lightweight Block Cipher

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on field-programmable-gate-array (FPGA) platform with and key lengths 32 64 bits. The critical features our architecture include parallelism, pipelining, dedicated controller. Parallelism splits digits data blocks into smaller segments. Then, we use each segmented in parallel for encryption decryption computations. Splitting helps reduce required clock cycles. A two-stage pipelining is used to shorten path improve frequency. controller implemented provide control functionalities. For performance evaluation design, report results two different cases Xilinx 7-series FPGA devices. case one, proposed can operate 382, 379, 388 MHz frequencies Kintex-7, Virtex-7, Artix-7 On same devices, utilized Slices are 49, 51, 50. one computation, design takes 16 minimum power consumption 172 mW Kintex-7 device. second case, targeted circuit frequency 50 synthesis With hardware resource utilization (51 Slices), least consumed 13.203 obtained proof-of-concept, validated NEXYS 4 Consequently, reveal that suitable many resource-constrained cryptographic applications.